Checking Correctness of Hardware RNG Architecture Specifications

Izdanje: Sinteza 2016 - International Scientific Conference on ICT and E-Business Related Research

DOI: 10.15308/Sinteza-2016-179-182

Link: https://doi.org/10.15308/Sinteza-2016-179-182

Apstrakt:
In this paper we will show one possible implementation of hardware randomness generator. The device in question is based on widely available electronic components comprised of double analogue comparator operating as a free running oscillator and RISC microcontroller used for post processing. Finally, we incorporated an USB interface for communication with the device in order to acquire and evaluate its practical use in cryptography. Data generated by our device show very good randomness characteristics and have high entropy.
Ključne reči: random number generators, cryptography, registers, FRO, noise
Kategorije objave: Radovi na konferenciji Sinteza 2016, Beograd, Srbija

Preuzimanje citata:

BibTeX format 
@article{article,
  author  = {I. Fermevc and S. Adamović}, 
  title   = {Checking Correctness of Hardware RNG Architecture Specifications},
  journal = {Sinteza 2016 - International Scientific Conference on ICT and E-Business Related Research},
  year    = 2016,
  doi     = {10.15308/Sinteza-2016-179-182}
}
RefWorks Tagged format 
RT Conference Proceedings
A1 Igor Fermevc
A1 Saša Adamović
T1 Checking Correctness of Hardware RNG Architecture Specifications
AD International Scientific Conference Sinteza, Beograd, Srbija
YR 2016
NO doi: 10.15308/Sinteza-2016-179-182
Unapred formatirani prikaz citata
I. Fermevc and S. Adamović, Checking Correctness of Hardware RNG Architecture Specifications, International Scientific Conference Sinteza, 2016, doi:10.15308/Sinteza-2016-179-182