FPGA Implementation of Throughput Increasing Techniques of the Binary Dividers

This paper deals with the binary dividers. A few different binary division algorithms are realized along with well known techniques for throughput increasing. Dividers are described in VHDL hardware description language and implemented in Altera and Xilinx FPGA devices. After classification of the binary division algorithms, radix2 restoring and radix2 nonrestoring algorithms are described with more details. The techniques for speed increasing (parallelism and pipelining) are applied after. All architectures are finally implemented in FPGA device and their comparison was done from the standpoint of speed and size (percentage of FPGA resources).